Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time a...
In this paper, we present a novel hardware architecture to achieve erosion and dilation with a large structuring element. We are proposing a modification of HGW algorithm with a bl...
Christophe Clienti, Michel Bilodeau, Serge Beucher
In this paper an embedded IDDQ testing architecture is presented that targets to overcome the excessive hardware overhead requirements in built-in current sensing based testing ap...
With widespread use of raster scan displays and the everincreasing desire for faster interactivity, higher image complexity, and higher resolution in displayed images, several tec...
Nader Gharachorloo, Satish Gupta, Robert F. Sproul...
A low-level graphics processor is assembled from a collection of hardwired functions of screen coordinates embedded directly in the display. Configuration of these functions is co...
Turner Whitted, James T. Kajiya, Erik Ruf, Ray Bit...