173 search results - page 13 / 35 » Scan Architecture With Align-Encode |
ASPDAC
2007
ACM
14 years 16 days ago
2007
ACM
Abstract-- This paper proposes a novel power-aware multifrequency wrapper architecture design to achieve at-speed testability. The trade-offs between power dissipation, scan time a...
ACIVS
2008
Springer
13 years 10 months ago
2008
Springer
In this paper, we present a novel hardware architecture to achieve erosion and dilation with a large structuring element. We are proposing a modification of HGW algorithm with a bl...
ISQED
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper an embedded IDDQ testing architecture is presented that targets to overcome the excessive hardware overhead requirements in built-in current sensing based testing ap...
SIGGRAPH
1989
ACM
14 years 18 days ago
1989
ACM
With widespread use of raster scan displays and the everincreasing desire for faster interactivity, higher image complexity, and higher resolution in displayed images, several tec...
EGH
2009
Springer
13 years 6 months ago
2009
Springer
A low-level graphics processor is assembled from a collection of hardwired functions of screen coordinates embedded directly in the display. Configuration of these functions is co...