The interconnect mechanisms (shared bus or crossbar) used in current chip-multiprocessors (CMPs) are expected to become a bottleneck that prevents these architectures from scaling...
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...
In order to achieve better scalability and reduce latency in handling user requests, many Web applications make extensive use of data replication through caches and Content Delive...
Bogdan C. Popescu, Maarten van Steen, Bruno Crispo...
This paper presents the software architecture and implementation of the problem solving environment (PSE) PELLPACK for modeling physical objects described by partial differential ...
Elias N. Houstis, John R. Rice, Sanjiva Weerawaran...
The global inter-networking infrastructure that has become essential for contemporary day-to-day computing and communication tasks, has also enabled the deployment of several large...