1263 search results - page 241 / 253 » Scatter-Add in Data Parallel Architectures |
CHES
2007
Springer
14 years 1 months ago
2007
Springer
Abstract. This paper discusses the state-of-the-art fast software implementation of block ciphers on Intel’s new microprocessor Core2, particularly concentrating on “bitslice i...
ICS
2009
Tsinghua U.
14 years 11 days ago
2009
Tsinghua U.
New static source routing algorithms for High Performance Computing (HPC) are presented in this work. The target parallel architectures are based on the commonly used fattree netw...
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
Transactional memory (TM) simplifies parallel programming by guaranteeing that transactions appear to execute atomically and in isolation. Implementing these properties includes p...
SIGMOD
2007
ACM
14 years 8 months ago
2007
ACM
Two trends are converging to make the CPU cost of a table scan a more important component of database performance. First, table scans are becoming a larger fraction of the query p...
PDCAT
2009
Springer
14 years 2 months ago
2009
Springer
Abstract—In this paper, a tool named CheCUDA is designed to checkpoint CUDA applications that use GPUs as accelerators. As existing checkpoint/restart implementations do not supp...