189 search results - page 37 / 38 » Scheduling Issues in Optimistic Parallelization |
ISCA
2010
IEEE
14 years 1 months ago
2010
IEEE
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
MICRO
2003
IEEE
14 years 1 months ago
2003
IEEE
Large instruction window processors achieve high performance by exposing large amounts of instruction level parallelism. However, accessing large hardware structures typically req...
EUROPAR
1999
Springer
14 years 24 days ago
1999
Springer
Processor cycle time continues to decrease faster than main memory access times, placing higher demands on cache memory hierarchy performance. To meet these demands, conventional ...
DEBS
2009
ACM
13 years 11 months ago
2009
ACM
Streaming data models have been shown to be useful in many applications requiring high-performance data exchange. Application-level overlay networks are a natural way to realize t...
ICS
2009
Tsinghua U.
14 years 3 months ago
2009
Tsinghua U.
To sustain emerging data-intensive scientific applications, High Performance Computing (HPC) centers invest a notable fraction of their operating budget on a specialized fast sto...