189 search results - page 6 / 38 » Scheduling Issues in Optimistic Parallelization |
ISPAN
2005
IEEE
14 years 4 months ago
2005
IEEE
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
MICRO
1992
IEEE
14 years 2 months ago
1992
IEEE
Software pipelining is an important instruction scheduling technique for efficiently overlapping successive iterations of loops and executing them in parallel. Modulo scheduling i...
ICPP
2008
IEEE
14 years 5 months ago
2008
IEEE
The issue queue (IQ) is a key microarchitecture structure for exploiting instruction-level and thread-level parallelism in dynamically scheduled simultaneous multithreaded (SMT) p...
DSD
2002
IEEE
14 years 3 months ago
2002
IEEE
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
HPCA
2004
IEEE
14 years 11 months ago
2004
IEEE
Design of wakeup-free issue queues is becoming desirable due to the increasing complexity associated with broadcast-based instruction wakeup. The effectiveness of most wakeup-free...