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DELTA
2004
IEEE
13 years 11 months ago
Scan Test of IP Cores in an ATE Environment
Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...
Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi
AIPS
2006
13 years 9 months ago
Predictive Planning for Supply Chain Management
Supply chains are ubiquitous in the manufacturing of many complex products. Traditionally, supply chains have been created through the intricate interactions of human representati...
David Pardoe, Peter Stone
ISPD
2000
ACM
126views Hardware» more  ISPD 2000»
14 years 9 days ago
A practical clock tree synthesis for semi-synchronous circuits
In this paper, we propose a new clock tree synthesis method for semi-synchronous circuits. A clock tree obtained by the proposed method is a multi-level multi-way clock tree such ...
Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui,...
DAC
1994
ACM
14 years 1 days ago
The Design of High-Performance Microprocessors at Digital
Today's high-performance single-chip CMOS microprocessors are the most complex and challenging chip designs ever implemented. To stay on the leading edge, Digital's micro...
Thomas F. Fox
CDC
2008
IEEE
14 years 2 months ago
Robust invariant set theory applied to networked buffer-level control
— A manufacturer producing several items keeps them into safety stocks (buffers) in order to supply an external stochastic demand without interruptions. We consider the classical...
Francesco Borrelli, Carmen Del Vecchio, Alessandra...