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IEEEPACT
2002
IEEE
14 years 17 days ago
A Framework for Parallelizing Load/Stores on Embedded Processors
Many modern embedded processors (esp. DSPs) support partitioned memory banks (also called X-Y memory or dual bank memory) along with parallel load/store instructions to achieve co...
Xiaotong Zhuang, Santosh Pande, John S. Greenland ...
IEEEPACT
2000
IEEE
14 years 22 hour ago
Region Formation Analysis with Demand-Driven Inlining for Region-Based Optimization
Region-based compilation repartitions a program into more desirable compilation units for optimization and scheduling, particularly beneficial for ILP architectures. With region-...
Tom Way, Ben Breech, Lori L. Pollock
HPCA
2001
IEEE
14 years 8 months ago
Automatically Mapping Code on an Intelligent Memory Architecture
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high...
Jaejin Lee, Yan Solihin, Josep Torrellas
ICS
1999
Tsinghua U.
13 years 12 months ago
Classifying load and store instructions for memory renaming
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary ...
IJFCS
2006
63views more  IJFCS 2006»
13 years 7 months ago
Critical Path Scheduling Parallel Programs on an Unbounded Number of Processors
In this paper we present an efficient algorithm for compile-time scheduling and clustering of parallel programs onto parallel processing systems with distributed memory, which is ...
Mourad Hakem, Franck Butelle