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» Scheduling Timed Modules for Correct Resource Sharing
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DATE
1999
IEEE
147views Hardware» more  DATE 1999»
13 years 12 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
NETWORKING
2004
13 years 9 months ago
Performance of Wireless Ad Hoc Networks under Balanced Fairness
Balanced fairness is a new resource sharing concept recently introduced by Bonald and Prouti`ere. We extend the use of this notion to wireless networks where the link capacities at...
Aleksi Penttinen, Jorma T. Virtamo
ICCAD
2007
IEEE
118views Hardware» more  ICCAD 2007»
14 years 4 months ago
Timing variation-aware high-level synthesis
—This work proposes a new yield computation technique dedicated to HLS, which is an essential component in timing variationaware HLS research field. The SSTAs used by the curren...
Jongyoon Jung, Taewhan Kim
PDP
2010
IEEE
13 years 12 months ago
Distributed Scheduler of Workflows with Deadlines in a P2P Desktop Grid
Scheduling large amounts of tasks in distributed computing platforms composed of millions of nodes is a challenging goal, even more in a fully decentralized way and with low overhe...
Javier Celaya, Unai Arronategui
AIPS
2000
13 years 9 months ago
Mixed-Initiative Resource Management: The AMC Barrel Allocator
In this paper, we describe the Barrel Allocator, a scheduling tool developed for day-to-day allocation and management of airlift and tanker resources at the USAF Air Mobility Comm...
Marcel A. Becker, Stephen F. Smith