57 search results - page 6 / 12 » Scheduling algorithms for unpredictably heterogeneous CMP ar... |
DATE
2004
IEEE
13 years 10 months ago
2004
IEEE
Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures ...
PC
2007
13 years 6 months ago
2007
We explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate con...
INFOCOM
1996
IEEE
13 years 11 months ago
1996
IEEE
In this paper, we develop a general model, called Latency-Rate servers (LR servers), for the analysis of traffic scheduling algorithms in broadband packet networks. The behavior of...
PPOPP
2010
ACM
14 years 1 months ago
2010
ACM
In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a singl...
ISPAN
2005
IEEE
14 years 8 days ago
2005
IEEE
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...