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» Scheduling under resource constraints using dis-equations
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ISVLSI
2005
IEEE
129views VLSI» more  ISVLSI 2005»
14 years 1 months ago
Reduction of Direct Tunneling Power Dissipation during Behavioral Synthesis of Nanometer CMOS Circuits
— Direct tunneling current is the major component of static power dissipation of a CMOS circuit for technology below 65nm, where the gate dielectric (SiO2) is very low. We intuit...
Saraju P. Mohanty, Ramakrishna Velagapudi, Valmiki...
DATE
1999
IEEE
162views Hardware» more  DATE 1999»
13 years 12 months ago
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis
In this paper, we present a system synthesis algorithm, called MOCSYN, which partitions and schedules embedded system specifications to intellectual property cores in an integrate...
Robert P. Dick, Niraj K. Jha
ICDCS
2007
IEEE
14 years 1 months ago
Overlay Node Placement: Analysis, Algorithms and Impact on Applications
Abstract— Overlay routing has emerged as a promising approach to improving performance and reliability of Internet paths. To fully realize the potential of overlay routing under ...
Sabyasachi Roy, Himabindu Pucha, Zheng Zhang, Y. C...
CORR
2010
Springer
163views Education» more  CORR 2010»
13 years 5 months ago
Design of QoS-aware Provisioning Systems
We present an architecture of a hosting system consisting of a set of hosted Web Services subject to QoS constraints, and a certain number of servers used to run users demand. The ...
Michele Mazzucco, Manuel Mazzara, Nicola Dragoni
GECCO
2003
Springer
103views Optimization» more  GECCO 2003»
14 years 26 days ago
Are Multiple Runs of Genetic Algorithms Better than One?
Abstract. There are conflicting reports over whether multiple independent runs of genetic algorithms (GAs) with small populations can reach solutions of higher quality or can fin...
Erick Cantú-Paz, David E. Goldberg