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EUROPAR
2001
Springer
14 years 1 months ago
Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse
Operand bypass logic might be one of the critical structures for future microprocessors to achieve high clock speed. The delay of the logic imposes the execution time budget to be ...
Toshinori Sato, Itsujiro Arita
LCPC
2001
Springer
14 years 1 months ago
Bridging the Gap between Compilation and Synthesis in the DEFACTO System
Abstract. The DEFACTO project - a Design Environment For Adaptive Computing TechnOlogy - is a system that maps computations, expressed in high-level languages such as C, directly o...
Pedro C. Diniz, Mary W. Hall, Joonseok Park, Byoun...
IEEEPACT
2000
IEEE
14 years 1 months ago
aSOC: A Scalable, Single-Chip Communications Architecture
As on-chip integration matures, single-chip system designers must not only be concerned with component-level issues such as performance and power, but also with onchip system-leve...
Jian Liang, Sriram Swaminathan, Russell Tessier
IPPS
2000
IEEE
14 years 1 months ago
Real-Time Transaction Processing Using Two-Stage Validation in Broadcast Disks
Conventional concurrency control protocols are inapplicable in mobile computing environments due to a number of constraints of wireless communications. In this paper, we design a p...
Kwok-Wa Lam, Victor C. S. Lee, Sang Hyuk Son
ISMVL
2000
IEEE
134views Hardware» more  ISMVL 2000»
14 years 1 months ago
The 2-SAT Problem of Regular Signed CNF Formulas
Signed conjunctive normal form (signed CNF) is a classical conjunctive clause form using a generalized notion of literal, called signed atom. A signed atom is an expression of the...
Bernhard Beckert, Reiner Hähnle, Felip Many&a...