84 search results - page 16 / 17 » Schemes for SR-Tree packing |
DAC
2002
ACM
14 years 8 months ago
2002
ACM
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-sca...
CGO
2008
IEEE
14 years 2 months ago
2008
IEEE
The recent trend in the processor industry of packing multiple processor cores in a chip has increased the importance of automatic techniques for extracting thread level paralleli...
GLOBECOM
2007
IEEE
14 years 1 months ago
2007
IEEE
— A relay selection approach has previously been shown to outperform repetition-based scheduling for both amplify-and-forward (AF) and decode-and-forward (DF) cooperative network...
LCN
2003
IEEE
14 years 27 days ago
2003
IEEE
Recently, IEEE 802.11 wireless networks have been widely deployed in public areas for mobile Internet services. In the public wireless LAN systems, paging function is necessary to...