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MICRO
2008
IEEE
84views Hardware» more  MICRO 2008»
14 years 2 months ago
A performance-correctness explicitly-decoupled architecture
Optimizing the common case has been an adage in decades of processor design practices. However, as the system complexity and optimization techniques’ sophistication have increas...
Alok Garg, Michael C. Huang
ICCD
2007
IEEE
182views Hardware» more  ICCD 2007»
14 years 2 months ago
Reducing leakage power in peripheral circuits of L2 caches
Leakage power has grown significantly and is a major challenge in microprocessor design. Leakage is the dominant power component in second-level (L2) caches. This paper presents t...
Houman Homayoun, Alexander V. Veidenbaum
ICMCS
2007
IEEE
169views Multimedia» more  ICMCS 2007»
14 years 2 months ago
Identifying Computer Graphics using HSV Color Model and Statistical Moments of Characteristic Functions
Computer graphics generated by advanced rendering software come to appear so photorealistic that it has become difficult for people to visually differentiate them from photographi...
Wen Chen, Yun Q. Shi, Guorong Xuan
IPPS
2007
IEEE
14 years 1 months ago
A Power-Aware Prediction-Based Cache Coherence Protocol for Chip Multiprocessors
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...
Ehsan Atoofian, Amirali Baniasadi
RTAS
2007
IEEE
14 years 1 months ago
Performance Debugging of Real-Time Systems Using Multicriteria Schedulability Analysis
Most of today’s real-time embedded systems consist of a heterogeneous mix of fully-programmable processors, fixed-function components or hardware accelerators, and partially-pr...
Unmesh D. Bordoloi, Samarjit Chakraborty