39 search results - page 2 / 8 » Search space reduction in high level synthesis by use of an ... |
VLSID
2009
IEEE
14 years 7 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
TCAD
2010
13 years 1 months ago
2010
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
ISVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
In this work, we present a genetic algorithm based automated circuit synthesis framework for passive analog circuits. A procedure is developed for the simultaneous generation of b...
CAV
2008
Springer
13 years 9 months ago
2008
Springer
The growing design-productivity gap has made designers shift toward using high-level languages like C, C++ and Java to do system-level design. High-Level Synthesis (HLS) is the pro...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
The use of nanometer technologies is making it increasingly important to consider transient characteristics of a circuit’s power dissipation (e.g., peak power, and power gradien...