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» Secure Configuration of Field Programmable Gate Arrays
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DATE
2010
IEEE
183views Hardware» more  DATE 2010»
14 years 18 days ago
Monolithically stackable hybrid FPGA
— The paper introduces novel field programmable gate array (FPGA) circuits based on hybrid CMOS/resistive switching device (memristor) technology and explores several logic archi...
Dmitri Strukov, Alan Mishchenko
ISCAS
2002
IEEE
89views Hardware» more  ISCAS 2002»
14 years 13 days ago
On segmented channel routability
We address the problem of checking the routability of segmented channels using satisfiability. The segmented channel routing problem arises in the context of row-based field progr...
William N. N. Hung, Xiaoyu Song, Alan J. Coppola, ...
IJCNN
2000
IEEE
13 years 12 months ago
Hardware Implementation of a PCA Learning Network by an Asynchronous PDM Digital Circuit
We have fabricated a PCA (Principal Component Analysis) learning network in a FPGA (Field Programmable Gate Array) by using an asynchronous PDM (Pulse Density Modulation) digital ...
Yuzo Hirai, Kuninori Nishizawa
TCAD
2008
112views more  TCAD 2008»
13 years 7 months ago
Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
Boolean matching is one of the enabling techniques for technology mapping and logic resynthesis of Field Programmable Gate Array (FPGA). SAT-based Boolean matching (SAT-BM) has bee...
Yu Hu, Victor Shih, Rupak Majumdar, Lei He
ERSA
2009
147views Hardware» more  ERSA 2009»
13 years 5 months ago
Fault Avoidance in Medium-Grain Reconfigurable Hardware Architectures
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
Kylan Robinson, José G. Delgado-Frias