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» Secure FPGA circuits using controlled placement and routing
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FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
14 years 2 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan
ICCTA
2007
IEEE
14 years 14 days ago
Faster Placer for Island-Style FPGAs
In this paper, we propose a placement method for islandstyle FPGAs, based on fast yet very good initial placement followed by refinement using ultra-low temperature Simulated Anne...
Pritha Banerjee, Susmita Sur-Kolay
ISCAS
2007
IEEE
128views Hardware» more  ISCAS 2007»
14 years 2 months ago
Collaborative Routing Architecture for FPGA
— In this paper we present the Collaborative Routing Architecture (CRA), a routing architecture specially designed to achieve high efficiency in hardware and competitive delay p...
Yaling Ma, Mingjie Lin
FPGA
2003
ACM
117views FPGA» more  FPGA 2003»
14 years 1 months ago
PipeRoute: a pipelining-aware router for FPGAs
We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-D...
Akshay Sharma, Carl Ebeling, Scott Hauck
FPGA
2010
ACM
250views FPGA» more  FPGA 2010»
14 years 5 months ago
Variation-aware placement for FPGAs with multi-cycle statistical timing analysis
Deep submicron processes have allowed FPGAs to grow in complexity and speed. However, such technology scaling has caused FPGAs to become more susceptible to the effects of process...
Gregory Lucas, Chen Dong, Deming Chen