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IOLTS
2003
IEEE
126views Hardware» more  IOLTS 2003»
14 years 3 months ago
Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits
A methodology for the synthesis of partially selfchecking multilevel logic circuits with low-cost paritybased concurrent error detection (CED) is described. A subset of the inputs...
Kartik Mohanram, Egor S. Sogomonyan, Michael G&oum...
MST
2006
120views more  MST 2006»
13 years 10 months ago
Exploiting Regularities for Boolean Function Synthesis
The "regularity" of a Boolean function can be exploited for decreasing its minimization time. It has already been shown that the notion of autosymmetry is a valid measure...
Anna Bernasconi, Valentina Ciriani, Fabrizio Lucci...
ESOP
2003
Springer
14 years 3 months ago
Using Controller-Synthesis Techniques to Build Property-Enforcing Layers
In complex systems, like robot plants, applications are built on top of a set of components, or devices. Each of them has particular individual constraints, and there are also log...
Karine Altisen, Aurélie Clodic, Florence Ma...
ICRA
2007
IEEE
124views Robotics» more  ICRA 2007»
14 years 4 months ago
Using Constrained Intuitionistic Linear Logic for Hybrid Robotic Planning Problems
— Synthesis of robot behaviors towards nontrivial goals often requires reasoning about both discrete and continuous aspects of the underlying domain. Existing approaches in build...
Uluc Saranli, Frank Pfenning
CCL
1994
Springer
14 years 2 months ago
Application of Constraint Logic Programming for VLSI CAD Tools
Abstract: This paper describes the application of CLP (constraint logic programming) to several digital circuit design problems. It is shown that logic programming together with ef...
Renate Beckmann, Ulrich Bieker, Ingolf Markhof