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ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
14 years 5 months ago
Application-specific customization of parameterized FPGA soft-core processors
Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are p...
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Fra...
CGO
2010
IEEE
14 years 3 months ago
Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bi
For memory constrained embedded systems code size is at least as important as performance. One way of increasing code density is to exploit compact instruction formats, e.g. ARM T...
Tobias J. K. Edler von Koch, Igor Böhm, Bj&ou...
CGO
2010
IEEE
14 years 3 months ago
Automatic creation of tile size selection models
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...
Tomofumi Yuki, Lakshminarayanan Renganarayanan, Sa...
ISPASS
2009
IEEE
14 years 3 months ago
The data-centricity of Web 2.0 workloads and its impact on server performance
Advances in network performance and browser technologies, coupled with the ubiquity of internet access and proliferation of users, have lead to the emergence of a new class of web...
Moriyoshi Ohara, Priya Nagpurkar, Yohei Ueda, Kazu...
ISPASS
2009
IEEE
14 years 3 months ago
GARNET: A detailed on-chip network model inside a full-system simulator
Until very recently, microprocessor designs were computation-centric. On-chip communication was frequently ignored. This was because of fast, single-cycle on-chip communication. T...
Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Nira...
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