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INFOCOM
2008
IEEE
14 years 1 months ago
Area Avoidance Routing in Distance-Vector Networks
Network routing may be required, under certain applications, to avoid certain areas (or nodes) These areas can be of potential security threat, possess poor quality or have other ...
Haim Zlatokrilov, Hanoch Levy
MICRO
2008
IEEE
138views Hardware» more  MICRO 2008»
14 years 1 months ago
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs
As the number of transistors integrated on a chip continues to increase, a growing challenge is accurately modeling performance in the early stages of processor design. Analytical...
Xi E. Chen, Tor M. Aamodt
DDECS
2007
IEEE
175views Hardware» more  DDECS 2007»
14 years 1 months ago
Analyzing Test and Repair Times for 2D Integrated Memory Built-in Test and Repair
—An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. A commonly used repair strategy is to equip memories with sp...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
ICDE
2007
IEEE
174views Database» more  ICDE 2007»
14 years 1 months ago
Adapting Partitioned Continuous Query Processing in Distributed Systems
Partitioned query processing is an effective method to process continuous queries with large stateful operators in a distributed systems. This method typically partitions input da...
Yali Zhu, Elke A. Rundensteiner
ICPP
2007
IEEE
14 years 1 months ago
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs
Three-dimensional Network-on-Chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length ...
Hiroki Matsutani, Michihiro Koibuchi, Hideharu Ama...