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MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
14 years 1 months ago
ASR: Adaptive Selective Replication for CMP Caches
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
Bradford M. Beckmann, Michael R. Marty, David A. W...
VLDB
2002
ACM
141views Database» more  VLDB 2002»
13 years 7 months ago
A Multi-version Cache Replacement and Prefetching Policy for Hybrid Data Delivery Environments
This paper introduces MICP, a novel multiversion integrated cache replacement and prefetching algorithm designed for efficient cache and transaction management in hybrid data deli...
André Seifert, Marc H. Scholl
ICCD
2004
IEEE
149views Hardware» more  ICCD 2004»
14 years 4 months ago
Adaptive Selection of an Index in a Texture Cache
For a specified application, there is an opportunity to improve cache performance by smart choosing of index bits of a cache. A texture cache for texture mapping of 3D computer gr...
Chun-Ho Kim, Lee-Sup Kim
IEEEINTERACT
2003
IEEE
14 years 20 days ago
Compiler-Directed Resource Management for Active Code Regions
Recent studies on program execution behavior reveal that a large amount of execution time is spent in small frequently executed regions of code. Whereas adaptive cache management ...
Ravikrishnan Sree, Alex Settle, Ian Bratt, Daniel ...
HPCA
2002
IEEE
14 years 10 days ago
Non-Vital Loads
As the frequency gap between main memory and modern microprocessor grows, the implementation and efficiency of on-chip caches become more important. The growing latency to memory ...
Ryan Rakvic, Bryan Black, Deepak Limaye, John Paul...