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ASPDAC
2006
ACM
117views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Signal-path driven partition and placement for analog circuit
This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three...
Di Long, Xianlong Hong, Sheqin Dong
DSD
2005
IEEE
105views Hardware» more  DSD 2005»
14 years 1 months ago
Improved Fault Emulation for Synchronous Sequential Circuits
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, R...
EURODAC
1994
IEEE
110views VHDL» more  EURODAC 1994»
13 years 11 months ago
Symbolic exploration of large circuits with enhanced forward/backward traversals
Symbolic state space exploration techniques for Finite State Machines (FSMs) are a major recent result in CAD for VLSI. Most of them are exact and based on forward traversal, but ...
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
DSD
2007
IEEE
83views Hardware» more  DSD 2007»
14 years 1 months ago
Hierarchical Identification of Untestable Faults in Sequential Circuits
Similar to sequential test pattern generation, the problem of identifying untestable faults in sequential circuits remains unsolved. Most of the previous works in untestability id...
Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kru...
SBCCI
2003
ACM
115views VLSI» more  SBCCI 2003»
14 years 25 days ago
Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits
Recycling was recently proposed as a system-level design technique to facilitate the building of complex System-on-Chips (SOC) by assembling pre-designed components. Recycling all...
Luca P. Carloni, Alberto L. Sangiovanni-Vincentell...