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MEMOCODE
2007
IEEE
14 years 1 months ago
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
Stephan Eggersglüß, Görschwin Fey,...
BC
2008
68views more  BC 2008»
13 years 7 months ago
Neural control of Caenorhabditis elegans forward locomotion: the role of sensory feedback
Abstract This paper presents a simple yet biologicallygrounded model for the neural control of Caenorhabditis elegans forward locomotion. We identify a minimal circuit within the C...
John Bryden, Netta Cohen
IOLTS
2008
IEEE
117views Hardware» more  IOLTS 2008»
14 years 2 months ago
Verification and Analysis of Self-Checking Properties through ATPG
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
Marc Hunger, Sybille Hellebrand
DAC
1994
ACM
13 years 11 months ago
Functional Test Generation for FSMs by Fault Extraction
Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques. Functional TPG alg...
Bapiraju Vinnakota, Jason Andrews
DT
2007
57views more  DT 2007»
13 years 7 months ago
Leakage Minimization Technique for Nanoscale CMOS VLSI
This paper proposes a new heuristic approach to determine the input pattern that minimizes leakage currents of nanometer CMOS circuits during sleep mode considering stack and fano...
Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Pa...