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ICCD
1995
IEEE
119views Hardware» more  ICCD 1995»
13 years 11 months ago
Extraction of finite state machines from transistor netlists by symbolic simulation
– This paper describes a new technique for extracting clock-level finite state machines(FSMs) from transistor netlists using symbolic simulation. The transistor netlist is prepr...
Manish Pandey, Alok Jain, Randal E. Bryant, Derek ...
DATE
2010
IEEE
156views Hardware» more  DATE 2010»
13 years 10 months ago
Defect aware X-filling for low-power scan testing
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads t...
S. Balatsouka, V. Tenentes, Xrysovalantis Kavousia...
DSD
2005
IEEE
96views Hardware» more  DSD 2005»
13 years 9 months ago
Improvement of the Fault Coverage of the Pseudo-Random Phase in Column-Matching BIST
Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of f...
Peter Filter, Hana Kubatova
ESANN
2003
13 years 9 months ago
Developmental pruning of synapses and category learning
After an initial peak, the number of synapses in mammalian cerebral cortex decreases in the formative period and throughout adult life. However, if synapses are taken to reflect ci...
Roberto Viviani, Manfred Spitzer
NIPS
2000
13 years 9 months ago
Finding the Key to a Synapse
Experimental data have shown that synapses are heterogeneous: different synapses respond with different sequences of amplitudes of postsynaptic responses to the same spike train. ...
Thomas Natschläger, Wolfgang Maass