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GLVLSI
2009
IEEE
201views VLSI» more  GLVLSI 2009»
13 years 10 months ago
Glitch-free design for multi-threshold CMOS NCL circuits
In this paper, a novel design is proposed for eliminating glitches and signal bounces during wake-up events that result from incorporating multi-threshold CMOS (MTCMOS) into async...
Ahmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia D...
SBCCI
2006
ACM
171views VLSI» more  SBCCI 2006»
14 years 1 months ago
Asynchronous circuit design on reconfigurable devices
This paper presents the design of asynchronous circuits on synchronous FPGAs and CPLDs. Different design styles have been investigated through the implementation of dual-rail full...
R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, An...
FPGA
2004
ACM
121views FPGA» more  FPGA 2004»
14 years 22 days ago
Highly pipelined asynchronous FPGAs
We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and sh...
John Teifel, Rajit Manohar
ICT
2004
Springer
127views Communications» more  ICT 2004»
14 years 22 days ago
An Interference Avoidance Technique for Ad Hoc Networks Employing Array Antennas
Array antennas have the potential to increase the capacity of wireless networks, but a distributed beamforming algorithm for maximizing the capacity in asynchronous, decentralized ...
T. Hunziker, Jacir Luiz Bordim, T. Ohira, Shinsuke...
INFOCOM
2010
IEEE
13 years 5 months ago
DAC: Distributed Asynchronous Cooperation for Wireless Relay Networks
—Cooperative relay is a communication paradigm that aims to realize the capacity of multi-antenna arrays in a distributed manner. However, the symbol-level synchronization requir...
Xinyu Zhang, Kang G. Shin