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ATS
2009
IEEE
162views Hardware» more  ATS 2009»
14 years 2 months ago
Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients
—A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit...
Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
DFT
2005
IEEE
109views VLSI» more  DFT 2005»
14 years 1 months ago
Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms
In this paper, we propose a system-level error tolerance scheme for systems where a linear transform is combined with quantization. These are key components in multimedia compress...
In Suk Chong, Antonio Ortega
ICCD
2002
IEEE
122views Hardware» more  ICCD 2002»
14 years 20 days ago
Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits
Concurrent detection of failures in analog circuits is becoming increasingly more important as safety-critical systems become more widespread. A methodology for the automatic desi...
Sule Ozev, Alex Orailoglu
STOC
2004
ACM
177views Algorithms» more  STOC 2004»
14 years 8 months ago
Lower bounds for linear degeneracy testing
Abstract. In the late nineties, Erickson proved a remarkable lower bound on the decision tree complexity of one of the central problems of computational geometry: given n numbers, ...
Nir Ailon, Bernard Chazelle
ICCAD
2006
IEEE
126views Hardware» more  ICCAD 2006»
14 years 4 months ago
Exploring linear structures of critical path delay faults to reduce test efforts
It has been shown that the delay of a target path can be composed linearly of other path delays. If the later paths are robustly testable (with known delay values), the target pat...
Shun-Yen Lu, Pei-Ying Hsieh, Jing-Jia Liou