605 search results - page 10 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
FPL
2004
Springer
13 years 11 months ago
2004
Springer
Pervasive networks with low-cost embedded 8-bit processors are set to change our day-to-day life. Public-key cryptography provides crucial functionality to assure security which is...
ECOOPW
1998
Springer
13 years 11 months ago
1998
Springer
Abstract. We introduce a collection of high performance kernels for basic linear algebra. The kernels encapsulate small xed size computations in order to provide building blocks fo...
HPCA
2004
IEEE
14 years 7 months ago
2004
IEEE
Design of wakeup-free issue queues is becoming desirable due to the increasing complexity associated with broadcast-based instruction wakeup. The effectiveness of most wakeup-free...
IEEEPACT
2008
IEEE
14 years 1 months ago
2008
IEEE
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
Implementing a custom hardware is not always feasible due to cost and time considerations. No instruction set computer (NISC) architecture is one of the promising direction to des...