605 search results - page 11 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
ICPPW
2006
IEEE
14 years 1 months ago
2006
IEEE
In retargeting loop-based code for multimedia instruction set extensions, a critical issue is that vector data types of mixed precision within a loop body complicate the paralleli...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
We are presenting a new concept of an application-specific processor that is capable of transmuting its instruction set according to non-predictive application behavior during run...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processo...
DCC
2007
IEEE
14 years 7 months ago
2007
IEEE
Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software de...
ICS
2005
Tsinghua U.
14 years 26 days ago
2005
Tsinghua U.
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...