605 search results - page 16 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
CAINE
2003
13 years 8 months ago
2003
In order to enhance the computer performance, nowadays microprocessors use Superscalar architecture. But the Superscalar architecture is unable to enhance the performance effectiv...
IEEEPACT
2002
IEEE
14 years 9 days ago
2002
IEEE
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
APCSAC
2003
IEEE
14 years 20 days ago
2003
IEEE
This paper proposes an approach for reducing access count to register-files based on operand data reuse. The key idea is to compare source and destination operands of the current ...
HPCN
1998
Springer
13 years 11 months ago
1998
Springer
This paper presents a new architecture organisation, the dynamically trace scheduled VLIW (DTSVLIW), that can be used to implement machines that execute the code of current RISC o...
IEEEPACT
2006
IEEE
14 years 1 months ago
2006
IEEE
Fast instruction decoding is a challenge for the design of CISC microprocessors. A well-known solution to overcome this problem is using a trace cache. It stores and fetches alrea...