605 search results - page 88 / 121 » Self-Timed Architecture of a Reduced Instruction Set Compute... |
IWOMP
2007
Springer
14 years 2 months ago
2007
Springer
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
MICRO
2010
IEEE
13 years 7 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
ISBI
2009
IEEE
14 years 3 months ago
2009
IEEE
In this paper we propose a fast method to detect spiculated lesions and architectural distortions in Digital Breast Tomosynthesis datasets. This approach relies on an a contrario ...
RTAS
2005
IEEE
14 years 2 months ago
2005
IEEE
Low-end embedded architectures, such as sensor nodes, have become popular in diverse fields, many of which impose real-time constraints. Currently, the Atmel Atmega processor fam...