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ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
14 years 6 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha
ITCC
2005
IEEE
14 years 3 months ago
Performance Analysis of Mobile Backbone Topology Synthesis Algorithm for Wireless Ad Hoc Networks
In this paper, we present a scalable fully distributed version of a Mobile Backbone Network Topology Synthesis Algorithm (MBN-TSA) for constructing and maintaining a dynamic backb...
Laura Huei-jiun Ju, Izhak Rubin
ISPD
2003
ACM
132views Hardware» more  ISPD 2003»
14 years 3 months ago
Architecture and synthesis for multi-cycle communication
For multi-gigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register ...
Jason Cong, Yiping Fan, Xun Yang, Zhiru Zhang
ENGL
2007
110views more  ENGL 2007»
13 years 9 months ago
A Comparative Study of Probabilistic and Worst-case Tolerance Synthesis
— The tolerance design directly influences the functionality of products and production costs. Tolerance synthesis is a procedure that distributes assembly tolerances between com...
Jirarat Teeravaraprug
ACSD
2010
IEEE
239views Hardware» more  ACSD 2010»
13 years 8 months ago
A Complete Synthesis Method for Block-Level Relaxation in Self-Timed Datapaths
Self-timed circuits present an attractive solution to the problem of process variation. However, implementing selftimed combinational logic can be complex and expensive. This pape...
W. B. Toms, David A. Edwards