Sciweavers

385 search results - page 53 / 77
» Semi-automatic Distributed Synthesis
Sort
View
ASAP
2007
IEEE
169views Hardware» more  ASAP 2007»
14 years 4 months ago
Reduced Delay BCD Adder
Financial and commercial applications use decimal data and spend most of their time in decimal arithmetic. Software implementation of decimal arithmetic is typically at least 100 ...
A. A. Bayrakci, A. Akkas
ASAP
2007
IEEE
144views Hardware» more  ASAP 2007»
14 years 4 months ago
A High-Throughput Programmable Decoder for LDPC Convolutional Codes
In this paper, we present and analyze a novel decoder architecture for LDPC convolutional codes (LDPCCCs). The proposed architecture enables high throughput and can be programmed ...
Marcel Bimberg, Marcos B. S. Tavares, Emil Mat&uac...
GECCO
2007
Springer
166views Optimization» more  GECCO 2007»
14 years 4 months ago
Scalable estimation-of-distribution program evolution
I present a new estimation-of-distribution approach to program evolution where distributions are not estimated over the entire space of programs. Rather, a novel representationbui...
Moshe Looks
ASAP
2006
IEEE
106views Hardware» more  ASAP 2006»
14 years 3 months ago
Throughput Optimized SHA-1 Architecture Using Unfolding Transformation
In this paper, we analyze the theoretical delay bound of the SHA-1 algorithm and propose architectures to achieve high throughput hardware implementations which approach this boun...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
ASAP
2006
IEEE
147views Hardware» more  ASAP 2006»
14 years 3 months ago
The Molen FemtoJava Engine
This paper presents the Molen FemtoJava engine that is extended with concepts taken from the Molen polymorphic processor. This allows for the existing FemtoJava to be augmented wi...
Júlio C. B. de Mattos, Stephan Wong, Luigi ...