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DAC
1999
ACM
14 years 23 days ago
Buffer Insertion with Accurate Gate and Interconnect Delay Computation
Buffer insertion has become a critical step in deep submicron design, and several buffer insertion/sizing algorithms have been proposed in the literature. However, most of these m...
Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
ICPP
1994
IEEE
14 years 17 days ago
A Distributed Cache Coherence Protocol for Hypercube Multiprocessors
- This paper proposes a distributed directory cache coherence protocol and compares the performance of the proposed protocol with fully mapped and single linked list protocols for ...
Yeimkuan Chang, Laxmi N. Bhuyan, Akhilesh Kumar
ECML
2007
Springer
14 years 11 days ago
Modeling Highway Traffic Volumes
Most traffic management and optimization tasks, such as accident detection or optimal vehicle routing, require an ability to adequately model, reason about and predict irregular an...
Tomás Singliar, Milos Hauskrecht
CIAC
2010
Springer
246views Algorithms» more  CIAC 2010»
13 years 12 months ago
Capacitated Confluent Flows: Complexity and Algorithms
A flow on a directed network is said to be confluent if the flow uses at most one outgoing arc at each node. Confluent flows arise naturally from destination-based routing. We stud...
Daniel Dressler and Martin Strehler
GLVLSI
2010
IEEE
154views VLSI» more  GLVLSI 2010»
13 years 10 months ago
Resource-constrained timing-driven link insertion for critical delay reduction
For timing-driven or yield-driven designs, non-tree routing has become more and more popular and additional loops provide the redundant paths to protect against the effect of the ...
Jin-Tai Yan, Zhi-Wei Chen