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MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
14 years 2 months ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
DATE
2004
IEEE
123views Hardware» more  DATE 2004»
14 years 5 days ago
On Concurrent Error Detection with Bounded Latency in FSMs
We discuss the problem of concurrent error detection (CED) with bounded latency in finite state machines (FSMs). The objective of this approach is to reduce the overhead of CED, a...
Sobeeh Almukhaizim, Petros Drineas, Yiorgos Makris
ICCV
2005
IEEE
14 years 10 months ago
Quasiconvex Optimization for Robust Geometric Reconstruction
Geometric reconstruction problems in computer vision are often solved by minimizing a cost function that combines the reprojection errors in the 2D images. In this paper, we show t...
Qifa Ke, Takeo Kanade
TCAD
2010
194views more  TCAD 2010»
13 years 3 months ago
Layout Decomposition Approaches for Double Patterning Lithography
Abstract--In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different ex...
Andrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Ya...
ASPDAC
2006
ACM
119views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Using speculative computation and parallelizing techniques to improve scheduling of control based designs
Recent research results have seen the application of parallelizing techniques to high-level synthesis. In particular, the effect of speculative code transformations on mixed contr...
Roberto Cordone, Fabrizio Ferrandi, Marco D. Santa...