171 search results - page 21 / 35 » Sensitivity analysis in decision circuits |
DAC
2008
ACM
14 years 10 months ago
2008
ACM
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
GLVLSI
2006
IEEE
14 years 3 months ago
2006
IEEE
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...
ISQED
2008
IEEE
14 years 3 months ago
2008
IEEE
The effects of random variations during the manufacturing process on devices can be simulated as a variation of transistor parameters. Device degradation, due to temperature or vo...
ISCAS
2003
IEEE
14 years 2 months ago
2003
IEEE
The design procedure of 2nd - and 3rd -order low-sensitivity lowpower allpole active resistance-capacitance (RC) filters, using the impedance tapering design method has already be...
COMPSAC
2003
IEEE
14 years 2 months ago
2003
IEEE
In this paper, we propose an algorithm to construct the Ordered Binary Decision Diagram (OBDD) representing the cut function of a terminal-pair network. The algorithm recognizes i...