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DELTA
2004
IEEE
13 years 11 months ago
Scan Test of IP Cores in an ATE Environment
Manufacturing test of chips made of multiple IP cores requires different techniques if ATE is used. As scan chains are commonly used as access paths to the DUT, ATE architectures ...
Luca Schiano, Yong-Bin Kim, Fabrizio Lombardi
JOT
2007
123views more  JOT 2007»
13 years 7 months ago
Towards a Tool Supporting Integration Testing of Aspect-Oriented Programs
Aspect-Oriented Programming is an emerging software engineering paradigm. It offers new constructs and tools improving separation of crosscutting concerns into single units called...
Philippe Massicotte, Linda Badri, Mourad Badri
TVLSI
2008
140views more  TVLSI 2008»
13 years 7 months ago
A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions
We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, ...
Jorge Campos, Hussain Al-Asaad
DT
2000
162views more  DT 2000»
13 years 7 months ago
RT-Level ITC'99 Benchmarks and First ATPG Results
Effective high-level ATPG tools are increasingly needed, as an essential element in the quest for reducing as much as possible the designer work on gate-level descriptions. We pro...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...
ICPR
2010
IEEE
13 years 10 months ago
A Reliability Assessment Paradigm for Automated Video Tracking Systems
Most existing performance evaluation methods concentrate on defining separate metrics over a wide range of conditions and generating standard benchmarking video sequences for exam...
Chung-Hao Chen, Yi Yao, Andreas Koschan, Mongi Abi...