A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions

We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, design error simulation, and model-directed test vector generation. We first present a control-based coverage measure that is aimed at exposing design errors that incorrectly set control signal values. We then describe MVP's high-level concurrent design error simulator that can handle various modeled design errors. We then present fundamental techniques and data structures for analyzing high-level circuit implementations and present various optimizations to speed-up the processing of data structures and consequently speed up MVP's overall test generation process. We next introduce a new automatic test vector generation technique for high-level hardware descriptions that generates a test sequence by efficiently solving constraints on multiple finite state machines. To speed up the test generation, MV...

• Type: Journal
• Year: 2008
• Where: TVLSI
• Authors: Jorge Campos, Hussain Al-Asaad
• Keywords: Design Errors, Test Generation, Test Vector Generation, TVLSI 2008