115 search results - page 14 / 23 » Sequential Circuit Verification Using Symbolic Model Checkin... |
ICST
2009
IEEE
13 years 5 months ago
2009
IEEE
Bounded model checking--as well as symbolic equivalence checking--are highly successful techniques in the hardware domain. Recently, bit-vector bounded model checkers like CBMC ha...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
State-based model checking methods comprise computing and storing reachable states, while stateless model checking methods directly reason about reachable paths using decision proc...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
We present an algorithm that checks behavioral consistency between an ANSI-C program and a circuit given in Verilog using Bounded Model Checking. Both the circuit and the program ...
CAV
2006
Springer
13 years 11 months ago
2006
Springer
We present an approach for applying symmetry reduction techniques to probabilistic model checking, a formal verification method for the quantitative analysis of systems with stocha...
CORR
2010
Springer
13 years 7 months ago
2010
Springer
We introduce streaming data string transducers that map input data strings to output data strings in a single left-to-right pass in linear time. Data strings are (unbounded) seque...