115 search results - page 3 / 23 » Sequential Circuit Verification Using Symbolic Model Checkin... |
FMCAD
1998
Springer
13 years 11 months ago
1998
Springer
We present a new approach to the verification of hardware systems with data dependencies using temporal logic symbolic model checking. As a benchmark we take Tomasulo's algori...
FMICS
2008
Springer
13 years 9 months ago
2008
Springer
Different approaches have been developed to mitigate the state space explosion of model checking techniques. Among them, symbolic verification techniques use efficient representati...
DATE
1999
IEEE
13 years 12 months ago
1999
IEEE
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Parametric representations used for symbolic simulation of circuits usually use BDDs. After a few steps of symbolic simulation, state set representation is converted from one para...
IJCAI
2003
13 years 9 months ago
2003
This paper addresses the formal verification of diagnosis systems. We tackle the problem of diagnosability: given a partially observable dynamic system, and a diagnosis system obs...