115 search results - page 4 / 23 » Sequential Circuit Verification Using Symbolic Model Checkin... |
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
In this paper, an approach to symbolic model checking of process networks is introduced. It is based on interval decision diagrams (IDDs), a representation of multi-valued functio...
ASYNC
1997
IEEE
13 years 11 months ago
1997
IEEE
Abstract-This paper describes the design and verification of a high-performance asynchronous differential equation solver benchmark circuit. The design has low control overhead whi...
ISQED
2007
IEEE
14 years 1 months ago
2007
IEEE
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we use...
ATAL
2004
Springer
13 years 11 months ago
2004
Springer
We present an approach to the problem of verification of epistemic properties of multi-agent systems by means of symbolic model checking. In particular, it is shown how to extend ...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...