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» Sequential circuits for program analysis
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TCAD
2010
121views more  TCAD 2010»
13 years 2 months ago
Translation Validation of High-Level Synthesis
The growing complexity of systems and their implementation into silicon encourages designers to look for model designs at higher levels of abstraction and then incrementally build ...
Sudipta Kundu, Sorin Lerner, Rajesh K. Gupta
DATE
2010
IEEE
168views Hardware» more  DATE 2010»
14 years 23 days ago
A new placement algorithm for the mitigation of multiple cell upsets in SRAM-based FPGAs
Modern FPGAs have been designed with advanced integrated circuit techniques that allow high speed and low power performance, joined to reconfiguration capabilities. This makes new...
Luca Sterpone, Niccolò Battezzati
CG
2005
Springer
13 years 7 months ago
Combining geometry and domain knowledge to interpret hand-drawn diagrams
One main challenge in building interpreters for hand-drawn sketches is the task of parsing a sketch to locate the individual symbols. Many existing pen-based systems avoid this pr...
Leslie Gennari, Levent Burak Kara, Thomas F. Staho...
ICCAD
2001
IEEE
124views Hardware» more  ICCAD 2001»
14 years 4 months ago
Partition-Based Decision Heuristics for Image Computation Using SAT and BDDs
Methods based on Boolean satisfiability (SAT) typically use a Conjunctive Normal Form (CNF) representation of the Boolean formula, and exploit the structure of the given problem ...
Aarti Gupta, Zijiang Yang, Pranav Ashar, Lintao Zh...
FMCAD
2004
Springer
14 years 1 months ago
Increasing the Robustness of Bounded Model Checking by Computing Lower Bounds on the Reachable States
Most symbolic model checkers are based on either Binary Decision Diagrams (BDDs), which may grow exponentially large, or Satisfiability (SAT) solvers, whose time requirements rapi...
Mohammad Awedh, Fabio Somenzi