18 search results - page 2 / 4 » Sequential equivalence checking using cuts |
DAC
2008
ACM
14 years 10 months ago
2008
ACM
C++ based verification methodologies are now emerging as the preferred method for SOC design. However most of the verification involving the C++ models are simulation based. The c...
CAV
2008
Springer
13 years 11 months ago
2008
Springer
Power gating is a technique for low power design in which whole sections of the chip are powered off when they are not needed, and powered back on when they are. Functional correct...
ICCAD
2002
IEEE
14 years 6 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
DAC
2007
ACM
14 years 1 months ago
2007
ACM
It has long been the practice to create models in C or C++ for architectural studies, software prototyping and RTL verification in the design of Systems-on-Chip (SoC). It is often...
ICLP
1995
Springer
14 years 1 months ago
1995
Springer
The semantics of constraint logic programming languages with coroutining facilities (\freeze," suspension, residuation, etc.) cannot be fully declarative; thus, an operationa...