69 search results - page 10 / 14 » Sequential synthesis using S1S |
CHARME
1995
Springer
13 years 11 months ago
1995
Springer
In this paper we present a method formodeling asynchronous digital circuits by timed automata. The constructed timed automata serve as \mechanical" and veri able objects for a...
ICCAD
2007
IEEE
13 years 11 months ago
2007
IEEE
Stepwise refinement is at the core of many approaches to synthesis and optimization of hardware and software systems. For instance, it can be used to build a synthesis approach for...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
DATE
2002
IEEE
14 years 21 days ago
2002
IEEE
The core computation in BDD-based symbolic synthesis and verification is forming the image and pre-image of sets of states under the transition relation characterizing the sequen...
BMCBI
2010
13 years 2 months ago
2010
Background: Ever since the ground-breaking work of Anfinsen et al. in which a denatured protein was found to refold to its native state, it has been frequently stated by the prote...