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» Set Constraints in Logic Programming
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ICCAD
1998
IEEE
95views Hardware» more  ICCAD 1998»
14 years 5 days ago
Efficient analog circuit synthesis with simultaneous yield and robustness optimization
This paper presents an efficient statistical design methodology that allows simultaneous sizing for performance and optimization for yield and robustness of analog circuits. The s...
Geert Debyser, Georges G. E. Gielen
AOSD
2007
ACM
13 years 12 months ago
A machine code model for efficient advice dispatch
The primary implementations of AspectJ to date are based on a compile- or load-time weaving process that produces Java byte code. Although this implementation strategy has been cr...
Ryan M. Golbeck, Gregor Kiczales
ICC
2007
IEEE
116views Communications» more  ICC 2007»
13 years 11 months ago
Robust Power Allocation for Amplify-and-Forward Relay Networks
Relay power allocation has been shown to provide substantial performance gain in wireless relay networks when perfect global channel state information (CSI) is available. In this p...
Tony Q. S. Quek, Moe Z. Win, Hyundong Shin, Marco ...
EUROMICRO
2004
IEEE
13 years 11 months ago
Using Academic Courses for Empirical Validation of Software Development Processes
Software Process Improvement needs sound empirical data gathered from a range of empirical studies such as controlled experiments or case studies. However, conducting empirical st...
Marcus Ciolkowski, Dirk Muthig, Jörg Rech
DAC
1995
ACM
13 years 11 months ago
A Transformation-Based Approach for Storage Optimization
High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-speci c integrated circuits (ASICs) and application-...
Wei-Kai Cheng, Youn-Long Lin