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IEEEPACT
2003
IEEE
14 years 2 months ago
Reactive Multi-Word Synchronization for Multiprocessors
Shared memory multiprocessor systems typically provide a set of hardware primitives in order to support synchronization. Generally, they provide single-word read-modify-write hard...
Phuong Hoai Ha, Philippas Tsigas
PODC
2010
ACM
14 years 19 days ago
Group mutual exclusion in O(log n) RMR
We present an algorithm to solve the GROUP MUTUAL EXCLUSION problem in the cache-coherent (CC) model. For the same problem in the distributed shared memory (DSM) model, Danek and ...
Vibhor Bhatt, Chien-Chung Huang
CGF
2011
13 years 3 months ago
A Parallel SPH Implementation on Multi-Core CPUs
This paper presents a parallel framework for simulating fluids with the Smoothed Particle Hydrodynamics (SPH) method. For low computational costs per simulation step, efficient ...
Markus Ihmsen, Nadir Akinci, Markus Becker, Matthi...
CODES
2011
IEEE
12 years 8 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
ISCA
2005
IEEE
90views Hardware» more  ISCA 2005»
14 years 2 months ago
Optimizing Replication, Communication, and Capacity Allocation in CMPs
Chip multiprocessors (CMPs) substantially increase capacity pressure on the on-chip memory hierarchy while requiring fast access. Neither private nor shared caches can provide bot...
Zeshan Chishti, Michael D. Powell, T. N. Vijaykuma...