202 search results - page 25 / 41 » Signal Processing Algorithms and Multiple-Valued Logic Desig... |
ISVLSI
2005
IEEE
14 years 1 months ago
2005
IEEE
high NRE cost. Therefore, general purpose programmable processors using software to perform various functions become more attractive since programmability can simplify system devel...
FP
1989
13 years 11 months ago
1989
This paper reports an explanation of an intricate algorithm in the terms of a potentially mechanisable rigorous-development method. It uses notations and techniques of Sheeran 1] ...
ICASSP
2008
IEEE
14 years 2 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
FPGA
2003
ACM
14 years 23 days ago
2003
ACM
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
In this paper we present a new fanout optimization algorithm which is particularly suitable for digital circuits designed with submicron CMOS technologies. Restricting the class o...