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» Signature Rollback - A Technique for Testing Robust Circuits
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ISCAS
2007
IEEE
128views Hardware» more  ISCAS 2007»
14 years 1 months ago
SAT-based ATPG for Path Delay Faults in Sequential Circuits
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
Stephan Eggersglüß, Görschwin Fey,...
DAC
2005
ACM
13 years 9 months ago
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits
Reliability of nanometer circuits is becoming a major concern in today’s VLSI chip design due to interferences from multiple noise sources as well as radiation-induced soft erro...
Chong Zhao, Yi Zhao, Sujit Dey
ICCAD
2007
IEEE
131views Hardware» more  ICCAD 2007»
14 years 3 months ago
Low-overhead design technique for calibration of maximum frequency at multiple operating points
— Determination of maximum operating frequencies (Fmax) during manufacturing test at different operating voltages is required to: (a) to ensure that, for a Dynamic Voltage and Fr...
Somnath Paul, Sivasubramaniam Krishnamurthy, Hamid...
VTS
2002
IEEE
162views Hardware» more  VTS 2002»
13 years 12 months ago
Self-Testing Second-Order Delta-Sigma Modulators Using Digital Stimulus
Single-bit second-order delta-sigma modulators are commonly used in high-resolution ADCs. Testing this type of modulator requires a high-resolution test stimulus, which is diffic...
Chee-Kian Ong, Kwang-Ting (Tim) Cheng
VLSID
2002
IEEE
127views VLSI» more  VLSID 2002»
14 years 7 months ago
Design of Asynchronous Controllers with Delay Insensitive Interface
Deep submicron technology calls for new design techniques, in which wire and gate delays are accounted to have equal or nearly equal effect on circuit behavior. Asynchronous speed...
Hiroshi Saito, Alex Kondratyev, Takashi Nanya