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ICCAD
2003
IEEE
152views Hardware» more  ICCAD 2003»
14 years 5 months ago
Leakage Power Optimization Techniques for Ultra Deep Sub-Micron Multi-Level Caches
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In deep sub-micron technology, the subthreshold leakage power is becoming...
Nam Sung Kim, David Blaauw, Trevor N. Mudge
CASES
2006
ACM
14 years 2 months ago
Adapting compilation techniques to enhance the packing of instructions into registers
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
Stephen Hines, David B. Whalley, Gary S. Tyson
ACL
2008
13 years 10 months ago
Self-Training for Biomedical Parsing
Parser self-training is the technique of taking an existing parser, parsing extra data and then creating a second parser by treating the extra data as further training data. Here ...
David McClosky, Eugene Charniak
BIOWIRE
2007
Springer
14 years 3 months ago
Beta Random Projection
Random projection (RP) is a common technique for dimensionality reduction under L2 norm for which many significant space embedding results have been demonstrated. In particular, r...
Yu-En Lu, Pietro Liò, Steven Hand
BMVC
2010
13 years 6 months ago
Iterative Hyperplane Merging: A Framework for Manifold Learning
We present a framework for the reduction of dimensionality of a data set via manifold learning. Using the building blocks of local hyperplanes we show how a global manifold can be...
Harry Strange, Reyer Zwiggelaar