109 search results - page 13 / 22 » Simplifying Instruction Issue Logic in Superscalar Processor... |
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
IEEEPACT
1999
IEEE
13 years 11 months ago
1999
IEEE
Trace cache, an instruction fetch technique that reduces taken branch penalties by storing and fetching program instructions in dynamic execution order, dramatically improves inst...
ISCA
1998
IEEE
13 years 11 months ago
1998
IEEE
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
CGO
2003
IEEE
14 years 24 days ago
2003
IEEE
A dynamic binary translation system for a co-designed virtual machine is described and evaluated. The underlying hardware directly executes an accumulator-oriented instruction set...
HIPEAC
2007
Springer
14 years 1 months ago
2007
Springer
In a dynamic reordering superscalar processor, the front-end fetches instructions and places them in the issue queue. Instructions are then issued by the back-end execution core. T...