109 search results - page 16 / 22 » Simplifying Instruction Issue Logic in Superscalar Processor... |
ISCA
2005
IEEE
14 years 1 months ago
2005
IEEE
Scaling feature size improves processor performance but increases each device’s susceptibility to defects (i.e., hard errors). As a result, fabrication technology must improve s...
ISHPC
2003
Springer
14 years 21 days ago
2003
Springer
Instruction issue consumes a large amount of energy in out of order processors, largely in the wakeup logic. Proposed solutions to the problem require prediction or additional hard...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
As the performance gap between processors and memory systems increases, the CPU spends more time stalled waiting for data from main memory. Critical long latency instructions, suc...
ISLPED
1998
ACM
13 years 11 months ago
1998
ACM
Register files (RF) represent a substantial portion of the energy budget in modern processors, and are growing rapidly with the trend towards wider instruction issue. The actual ...
ARCS
2006
Springer
13 years 11 months ago
2006
Springer
While trace cache, value prediction, and prefetching have been shown to be effective in the single-threaded superscalar, there has been no analysis of these techniques in a Simulta...