The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring...
Chrysostomos Nicopoulos, Dongkook Park, Jongman Ki...
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
Katherine E. Coons, Xia Chen, Doug Burger, Kathryn...
Abstract. We explore a new general-purpose heuristic for nding highquality solutions to hard optimization problems. The method, called extremal optimization, is inspired by self-or...
Stefan Boettcher, Allon G. Percus, Michelangelo Gr...
In the current Internet picture more than 70% of the hosts are located behind Network Address Translators (NATs). This is not a problem in the client/server paradigm. However, the...
—Inter-cell interference (ICI) mitigation is always a big challenge issue in cellular systems. In this work we propose an Enhanced Fractional Frequency Reuse (EFFR) scheme combin...